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Sr. Engineer - ASIC Chip/Block Physical Designer #19000071 San Jose , CA 95134 Posted: 09/08/2020 Employment Type: Direct Placement Category: Semiconductor Processors Job Number: 87039 Job Description We are looking for a Sr. Engineer in ASIC Chip/Block Physical Design for a client of ours San Jose, CA. You ll be a chip/block designer, who will do hands-on physical design takes for top-level SO...
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Job Description SummaryJob DescriptionAs a member of the BD Biosciences San Jose Electrical Engineering Research & Development team, you will be responsible for the design and support of sophisticated medical instrumentation. This equipment includes technology from every major area of science and engineering.The Electrical Engineering Research & Development team is responsible for high-speed ce...
Physical Design Engineer Santa Clara Valley (Cupertino) , California , United States Hardware Summary Posted: Nov 17, 2020 Role Number: 200201398 At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physi...
Sr. Functional Safety Engineer - SPG Santa Clara Valley (Cupertino) , California , United States Hardware Summary Posted: Aug 4, 2020 Role Number: 200184423 Apple's Special Projects Group is looking for an exceptional engineer with experience in product safety analysis, requirements engineering, hazard and risk analysis, and multi-disciplinary product development experience in safety critical m...
Key Qualifications:5+ years of experience in RF/Analog CMOS designSolid fundamentals in RF CMOS implementation of circuit building blocks including LNA, mixers, VCO, LO, and Power Amplifier.Experience designing RF transceivers in deep sub-micron RFCMOS technology.Familiarity with various RF transceiver architectures and their trade-offs, as well as demonstrated capability to work with digital d...
DescriptionSK hynix memory solutions America Inc. (SKHMS America) provides industry-leading controller hardware, advanced flash management systems, and firmware for NAND and post 2D-NAND based storage solutions spanning Enterprise, Client and Mobile market segments. We are part of the world's top tier semiconductor supplier, SK hynix, offering Dynamic Random Access Memory chips (DRAM), Flash me...
If you are a Sr. Verification Engineer with 4+ years experience, please read on! Job Title: Sr. Verification Engineer (image processing/ video compression) Job Location: Santa Clara, CA Salary: $150,000- 175,000 + RSU's Requirements: UVM, systemverilog, C++ Top Reasons to Work with Us Based in Santa Clara, we are a leading developer of low-power, high-definition and Ultra HD video compression a...
Juniper Networks is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. We believe in excellence and we strive to achieve that through employee motivation, training and teamwork within a collaborative and innovative culture. This role is a Silicon Architect for next-generation Networking ASICs.Resp...
Company DescriptionLeading Semiconductor IndustryJob DescriptionDescription:SR. Design EngineerSkills required, not limited to the following8+ Years of ExperienceExperience in the following aspects of Front End Design1. Knowledge of HDK and ACE environments a huge positive and advantage2. RTL Coding3. System Verilog and Verilog LRM specific knowledge4. Handling of Packages, Structs and other co...
Date: Jul 15, 2021 Location: Pleasanton, CA, US Company: Teleflex Expected Travel: Up to 10% Requisition ID: 3976 About Teleflex Incorporated Teleflex is a global provider of clinically effective medical technologies designed to improve the health and quality of people's lives. We apply purpose driven innovation - a relentless pursuit of identifying unmet clinical needs - to benefit patients an...
Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 5 years of physical design experience. Experience with one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC). Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations. Preferred qualifications: Fundamentals of computer architectur...
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